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Fixes required for Solang#10

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dmakarov merged 2 commits intoanza-xyz:solana-rustc/11.0-2021-01-05from
seanyoung:solang-fixes
Apr 13, 2021
Merged

Fixes required for Solang#10
dmakarov merged 2 commits intoanza-xyz:solana-rustc/11.0-2021-01-05from
seanyoung:solang-fixes

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Comment thread clang/lib/Basic/Targets/BPF.h Outdated
Comment thread lld/tools/lld/lld.cpp Outdated
@dmakarov
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I add the prefix [SOL][BPF] to every commit message, to distinguish visually the commits that are Solana specific, so I don't miss them when I update the source tree to a new snapshot of llvm-project. It would be nice if your commit message had this prefix too ([BPF] may be not applicable to clang or lld changes, but I would appreciate having the [SOL] prefix).

Every time Solang tries to link a web-assembly file in-process, the linker
re-inits llvm which is not thread-safe with the rest of solang.

Signed-off-by: Sean Young <sean@mess.org>
@seanyoung
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I've updated the commit messages.

@dmakarov
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LGTM. Let's wait for the CI checks to finish (it'll take some time), and then this can be merged. Thank you.

@seanyoung seanyoung changed the title llvm fixes required for Solang Fixes required for Solang Apr 13, 2021
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seanyoung commented Apr 13, 2021

Looks like all CI checks have passed

@dmakarov dmakarov merged this pull request into anza-xyz:solana-rustc/11.0-2021-01-05 Apr 13, 2021
dmakarov pushed a commit that referenced this pull request Apr 13, 2021
* [SOL] Make lld thread-safe with llvm when used in-process

Every time Solang tries to link a web-assembly file in-process, the linker
re-inits llvm which is not thread-safe with the rest of solang.

Signed-off-by: Sean Young <sean@mess.org>

* [SOL][BPF] Enable the _ExtInt extension on the BPF Target for Solana

Signed-off-by: Sean Young <sean@mess.org>
LucasSte pushed a commit to LucasSte/llvm-project that referenced this pull request Jan 9, 2026
…izer (llvm#173734)

This patch extends the AArch64ConditionOptimizer pass to handle CSINC
instructions within a single basic block, complementing the existing
cross-block branch optimization.

The optimization finds two CMP+CSINC pairs comparing the same register
with immediates differing by 1, and adjusts one comparison to enable CSE
to eliminate the redundant CMP instruction.

Example transformation:
```
  cmp  w8, anza-xyz#10
  csinc w9, w0, w1, gt     ; w9 = (w8 > 10) ? w0 : w1+1
  cmp  w8, anza-xyz#9              ; Removed by CSE after adjustment
  csinc w10, w0, w1, gt    ; w10 = (w8 > 9) ? w0 : w1+1
```

After optimization:
```
  cmp  w8, anza-xyz#10
  csinc w9, w0, w1, gt     ; w9 = (w8 > 10) ? w0 : w1+1
  csinc w10, w0, w1, ge    ; w10 = (w8 >= 10) ? w0 : w1+1
```

The existing cross-block logic has also been extracted into its own
method.

Any feedback on code quality and better practices is highly welcome.

Co-authored-by: Hussam Alhassan <hsm.link@proton.me>
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2 participants